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the uc3842b/3b/4b/5b, series are high performance fixed frequency current mode controllers. they are specifically designed for offline and dctodc converter applications offering the designer a costeffective solution with minimal external components. these integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power mosfet. also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cyclebycycle current limiting, programmable output deadtime, and a latch for single pulse metering. these devices are available in an 8pin dualinline and surface mount (so8) plastic package as well as the 14pin plastic surface mount (so14). the so14 package has separate power and ground pins for the totem pole output stage. the ucx842b has uvlo thresholds of 16 v (on) and 10 v (off), ideally suited for offline converters. the ucx843b is tailored for lower voltage applications having uvlo thresholds of 8.5 v (on) and 7.6 v (off). ? trimmed oscillator for precise frequency control ? oscillator frequency guaranteed at 250 khz ? current mode operation to 500 khz ? automatic feed forward compensation ? latching pwm for cyclebycycle current limiting ? internally trimmed reference with undervoltage lockout ? high current totem pole output ? undervoltage lockout with hysteresis ? low startup and operating current figure 1. simplified block diagram 5.0v reference latching pwm v cc undervoltage lockout oscillator error amplifier 7(12) v c 7(11) output 6(10) power ground 5(8) 3(5) current sense input v ref 8(14) 4(7) 2(3) 1(1) gnd 5(9) r t /c t voltage feedback input r r + - v ref undervoltage lockout output compensation pin numbers in parenthesis are for the d suffix so-14 package. v cc 14 1 1 8 compensation nc voltage feedback nc current sense nc r t /c t compensation voltage feedback current sense r t /c t v ref v ref nc v cc v c output gnd power ground v cc output gnd (top view) 8 7 6 5 1 2 3 4 1 2 3 4 14 13 12 11 5 6 7 10 9 8 (top view) 1 8 uc3842b/3b/4b/5b,uc2842b/3b page 1/16 @ 2010 copyright by american first semiconductor high performance current mode controllers general description features package outline dip-8 sop-8 sop-14 pin connections
maximum ratings rating symbol value unit bias and driver voltages (zero series impedance, see also total device spec) v cc , v c 30 v total power supply and zener current (i cc + i z ) 30 ma output current, source or sink (note 1) i o 1.0 a output energy (capacitive load per cycle) w 5.0 m j current sense and voltage feedback inputs v in 0.3 to + 5.5 v error amp output sink current i o 10 ma power dissipation and thermal characteristics d suffix, plastic package, so14 case 751a maximum power dissipation @ t a = 25 c thermal resistance, junctiontoair d1 suffix, plastic package, so8 case 751 maximum power dissipation @ t a = 25 c thermal resistance, junctiontoair n suffix, plastic package, case 626 maximum power dissipation @ t a = 25 c thermal resistance, junctiontoair p d r q ja p d r q ja p d r q ja 862 145 702 178 1.25 100 mw c/w mw c/w w c/w operating junction temperature t j +150 c operating ambient temperature uc3842b/3b/4b/5b uc2842b/3b t a 0 to + 70 25 to + 85 c storage temperature range t stg 65 to +150 c electrical characteristics (v cc = 15 v [note 2], r t = 10 k, c t = 3.3 nf. for typical values t a = 25 c, for min/max values t a is the operating ambient temperature range that applies [note 3], unless otherwise noted.) uc284xb uc384xb characteristics symbol min typ max min typ max unit reference section reference output voltage (i o = 1.0 ma, t j = 25 c) v ref 4.95 5.0 5.05 4.9 5.0 5.1 v line regulation (v cc = 12 v to 25 v) reg line 2.0 20 6.0 20 mv load regulation (i o = 1.0 ma to 20 ma) reg load 3.0 25 6.0 25 mv temperature stability t s 0.2 0.2 mv/ c total output variation over line, load, and temperature v ref 4.9 5.1 4.82 5.18 v output noise voltage (f = 10 hz to 10 khz, t j = 25 c) v n 50 50 m v long term stability (t a = 125 c for 1000 hours) s 5.0 5.0 mv output short circuit current i sc 30 85 180 30 100 180 ma oscillator section frequency t j = 25 c t a = t low to t high t j = 25 c (r t = 6.2 k, c t = 1.0 nf) f osc 49 48 225 52 250 55 56 275 47 47 225 50 52 250 55 56 275 khz frequency change with voltage (v cc = 12 v to 25 v) d f osc / d v 0.2 1.0 0.2 1.0 % frequency change with temperature, t a = t low to t high d f osc / d t 1.0 0.5 % oscillator voltage swing (peaktopeak) v osc 1.6 1.6 v discharge current (v osc = 2.0 v) t j = 25 c t a = t low to t high (uc284xb, uc384xb) t a = t low to t high i dischg 7.8 7.5 8.3 8.8 8.8 7.8 7.6 8.3 8.8 8.8 ma 1. maximum package power dissipation limits must be observed. 2. adjust v cc above the startup threshold before setting to 15 v. 3. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. t low = 0 c for uc3842b/3b/4b/5b; 25 c for uc2842b/3b t high = +70 c for uc3842b/3b/4b/5b; +85 c for uc2842b/3b page 2/16 www.first-semi.com uc3842b/3b/4b/5b,uc2842b/3b
electrical characteristics (v cc = 15 v [note 4], r t = 10 k, c t = 3.3 nf. for typical values t a = 25 c, for min/max values t a is the operating ambient temperature range that applies [note 5], unless otherwise noted.) uc284xb uc384xb characteristics symbol min typ max min typ max unit error amplifier section voltage feedback input (v o = 2.5 v) v fb 2.45 2.5 2.55 2.42 2.5 2.58 v input bias current (v fb = 5.0 v) i ib 0.1 1.0 0.1 2.0 m a open loop voltage gain (v o = 2.0 v to 4.0 v) a vol 65 90 65 90 db unity gain bandwidth (t j = 25 c) bw 0.7 1.0 0.7 1.0 mhz power supply rejection ratio (v cc = 12 v to 25 v) psrr 60 70 60 70 db output current sink (v o = 1.1 v, v fb = 2.7 v) source (v o = 5.0 v, v fb = 2.3 v) i sink i source 2.0 0.5 12 1.0 2.0 0.5 12 1.0 ma output voltage swing high state (r l = 15 k to ground, v fb = 2.3 v) low state (r l = 15 k to v ref , v fb = 2.7 v) (uc284xb, uc384xb) v oh v ol 5.0 6.2 0.8 1.1 5.0 6.2 0.8 1.1 v current sense section current sense input voltage gain (notes 6 & 7) (uc284xb, uc384xb) a v 2.85 3.0 3.15 2.85 3.0 3.15 v/v maximum current sense input threshold (note 6) (uc284xb, uc384xb) v th 0.9 1.0 1.1 0.9 1.0 1.1 v power supply rejection ratio (v cc = 12 v to 25 v, note 6) psrr 70 70 db input bias current i ib 2.0 10 2.0 10 m a propagation delay (current sense input to output) t plh(in/out) 150 300 150 300 ns output section output voltage low state (i sink = 20 ma) (i sink = 200 ma) (uc284xb, uc384xb) high state (i source = 20 ma) (uc284xb, uc384xb) (i source = 200 ma) v ol v oh 13 12 0.08 1.4 13.5 13.0 0.4 2.2 13 12 0.08 1.4 13.5 13.0 0.4 2.2 v output voltage with uvlo activated (v cc = 6.0 v, i sink = 1.0 ma) v ol(uvlo) 0.1 1.1 0.1 1.1 v output voltage rise time (c l = 1.0 nf, t j = 25 c) t r 45 150 45 150 ns output voltage fall time (c l = 1.0 nf, t j = 25 c) t f 35 150 35 150 ns undervoltage lockout section startup threshold (v cc ) ucx842b/4b ucx843b/5b v th 15 7.8 16 8.4 17 9.0 14.5 7.8 16 8.4 17.5 9.0 v minimum operating voltage after turnon (v cc ) ucx842b/4b ucx843b/5b v cc(min) 9.0 7.0 10 7.6 11 8.2 8.5 7.0 10 7.6 11.5 8.2 v 4. adjust v cc above the startup threshold before setting to 15 v. 5. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. t low = 0 c for uc3842b/3b/4b/5b; 25 c for uc2842b/3b t high = +70 c for uc3842b/3b/4b/5b; +85 c for uc2842b/3b 6. this parameter is measured at the latch trip point with v fb = 0 v. 7. comparator gain is defined as: a v d v output compensation d v current sense input uc3842b/3b/4b/5b,uc2842b/3b page 3/16 www.first-semi.com
electrical characteristics (v cc = 15 v [note 8], r t = 10 k, c t = 3.3 nf, for typical values t a = 25 c, for min/max values t a is the operating ambient temperature range that applies [note 9], unless otherwise noted.) uc284xb uc384xb, bv characteristics symbol min typ max min typ max unit pwm section duty cycle maximum (uc284xb, uc384xb) maximum minimum dc (max) dc (min) 94 96 0 94 96 0 % total device power supply current startup (v cc = 6.5 v for ucx843b, startup (v cc 14 v for ucx842b) operating (note 8) i cc + i c 0.17 13 0.3 17 0.17 13 0.3 17 ma power supply zener voltage (i cc = 25 ma) v z 30 36 30 36 v 8. adjust v cc above the startup threshold before setting to 15 v. 9. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. t low = 0 c for uc3842b/3b/4b/5b; 25 c for uc2842b/3b t high = +70 c for uc3842b/3b/4b/5b; +85 c for uc2842b/3b 0.8 2.0 5.0 8.0 20 50 80 r t , timing resistor (k ) w 1.0 m 500 k 200 k 100 k 50 k 20 k 10 k f osc , oscillator frequency (khz) v cc = 15 v t a = 25 c figure 2. timing resistor versus oscillator frequency figure 3. output deadtime versus oscillator frequency 1.0 m 500 k 200 k 100 k 50 k 20 k 10 k f osc , oscillator frequency (khz) 1.0 2.0 5.0 10 20 50 100 % dt, percent output deadtime 1 2 figure 4. oscillator discharge current versus temperature figure 5. maximum output duty cycle versus timing resistor , discharge current (ma) 7.0 -55 t a , ambient temperature ( c) -25 0 25 50 75 100 125 dischg i 7.5 8.0 8.5 9.0 v cc = 15 v v osc = 2.0 v , maximum output duty cycle (%) max d 40 0.8 r t , timing resistor (k w ) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 50 60 70 80 90 100 i dischg = 7.5 ma v cc = 15 v c t = 3.3 nf t a = 25 c 1. c t = 10 nf 2. c t = 5.0 nf 3. c t = 2.0 nf 4. c t = 1.0 nf 5. c t = 500 pf 6. c t = 200 pf 7. c t = 100 pf 5 i dischg = 8.8 ma 7 3 6 4 v cc = 15 v t a = 25 c uc3842b/3b/4b/5b,uc2842b/3b page 4/16 www.first-semi.com
figure 6. error amp small signal transient response figure 7. error amp large signal transient response figure 8. error amp open loop gain and phase versus frequency figure 9. current sense input threshold versus error amp output voltage figure 10. reference voltage change versus source current figure 11. reference short circuit current versus temperature -20 a vol , open loop voltage gain (db) 10 m 10 f, frequency (hz) gain phase v cc = 15 v v o = 2.0 v to 4.0 v r l = 100 k t a = 25 c 0 30 60 90 120 150 180 100 1.0 k 10 k 100 k 1.0 m 0 20 40 60 80 100 , excess phase (degrees) f 0 v o , error amp output voltage (v) 0 , current sense input threshold (v) v th 0.2 0.4 0.6 0.8 1.0 1.2 2.0 4.0 6.0 8.0 v cc = 15 v t a = 25 c t a = -55 c t a = 125 c ???? v cc = 15 v ??? ??? t a = -55 c ???? ???? t a = 25 c , reference voltage change (mv) -16 0 i ref , reference source current (ma) 20 40 60 80 100 120 ref v -12 -8.0 -4.0 0 d -20 -24 ???? ???? t a = 125 c ??? ??? v cc = 15 v r l 0.1 w , reference short circuit current (ma) sc i 50 -55 t a , ambient temperature ( c) -25 0 25 50 75 100 125 70 90 110 1.0 m s/div 0.5 m s/div 20 mv/div 20 mv/div 2.55 v 2.50 v 2.45 v 3.0 v 2.5 v 2.0 v v cc = 15 v a v = -1.0 t a = 25 c v cc = 15 v a v = -1.0 t a = 25 c uc3842b/3b/4b/5b,uc2842b/3b page 5/16 www.first-semi.com
???? ???? sink saturation (load to v cc ) ???? t a = -55 c ??? ??? v cc ????? ????? source saturation (load to ground) 0 v sat , output saturation voltage (v) 800 0 i o , output load current (ma) 200 400 600 1.0 2.0 3.0 -2.0 -1.0 0 ??? ??? t a = -55 c figure 12. reference load regulation figure 13. reference line regulation figure 14. output saturation voltage versus load current figure 15. output waveform figure 16. output cross conduction figure 17. supply current versus supply voltage ??? t a = 25 c ???? ???? ???? r t = 10 k c t = 3.3 nf v fb = 0 v i sense = 0 v t a = 25 c , supply current (ma) cc i 0 0 v cc , supply voltage (v) 10 20 30 40 5 10 15 20 25 ucx843b ucx842b ???? t a = 25 c ?? ?? gnd ????? ????? ????? v cc = 15 v 80 m s pulsed load 120 hz rate 2.0 ms/div 2.0 ms/div v cc = 15 v i o = 1.0 ma to 20 ma t a = 25 c v cc = 12 v to 25 t a = 25 c , output voltage change (2.0 mv/d i v o d , output voltage change (2.0 mv/d i v o d v cc = 30 v c l = 15 pf t a = 25 c v cc = 15 v c l = 1.0 nf t a = 25 c 50 ns/div 100 ns/div 100 ma/div 20 v/div 90% 10% , output voltage o v , supply current cc i uc3842b/3b/4b/5b,uc2842b/3b page 6/16 www.first-semi.com
pin function description pin 8pin 14pin function description 1 1 compensation this pin is the error amplifier output and is made available for loop compensation. 2 3 voltage feedback this is the inverting input of the error amplifier. it is normally connected to the switching power supply output through a resistor divider. 3 5 current sense a voltage proportional to inductor current is connected to this input. the pwm uses this information to terminate the output switch conduction. 4 7 r t /c t the oscillator frequency and maximum output duty cycle are programmed by connecting resistor r t to v ref and capacitor c t to ground. operation to 500 khz is possible. 5 gnd this pin is the combined control circuitry and power ground. 6 10 output this output directly drives the gate of a power mosfet. peak currents up to 1.0 a are sourced and sunk by this pin. 7 12 v cc this pin is the positive supply of the control ic. 8 14 v ref this is the reference output. it provides charging current for capacitor c t through resistor r t . 8 power ground this pin is a separate power ground return that is connected back to the power source. it is used to reduce the effects of switching transient noise on the control circuitry. 11 v c the output high state (v oh ) is set by the voltage applied to this pin. with a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. 9 gnd this pin is the control circuitry ground return and is connected back to the power source ground. 2,4,6,13 nc no connection. these pins are not internally connected. uc3842b/3b/4b/5b,uc2842b/3b page 7/16 www.first-semi.com
+ - reference regulator v cc uvlo + - v ref uvlo 3.6v 36v s r q internal bias + 1.0ma oscillator 2.5v r r r 2r error amplifier voltage feedback input output/ compensation current sense comparator 1.0v v cc 7(12) gnd 5(9) v c 7(11) output 6(10) power ground 5(8) current sense input 3(5) r s q1 v cc v in 1(1) 2(3) 4(7) 8(14) r t c t v ref = sink only positive true logic pin numbers adjacent to terminals are for the 8-pin dual-in-line package. pin numbers in parenthesis are for the d suffix so-14 package. figure 18. representative block diagram figure 19. timing diagram large r t /small c t small r t /large c t pwm latch (see text) capacitor c t latch set" input output/ compensation current sense input latch reset" input output uc3842b/3b/4b/5b,uc2842b/3b page 8/16 www.first-semi.com
figure 20. continuous current waveforms 2(3) ea bias + osc r r r 2r 5(9) 1(1) 4(7) 8(14) r t c t v ref 0.01 the diode clamp is required if the sync amplitude is large enough to cause the bottom side of c t to go more than 300 mv below ground. external sync input 47 + r r r 2r bias osc ea 5(9) 1(1) 2(3) 4(7) 8(14) to additional ucx84xbs r s q 8 4 6 5 2 1 c 3 7 r a r b 5.0k 5.0k 5.0k mc1455 f 1.44 (r a 2r b )c d (max) r b r a 2r b + - 5.0v ref + - s r q bias + osc r r r 2r ea 1.0v 5(9) 7(11) 6(10) 5(8) 3(5) r s q1 v cc v in 1(1) 2(3) 4(7) 8(14) r 1 v clamp r 2 7(12) comp/latch 1.0 ma i pk(max) v clamp r s where: 0 v clamp 1.0 v v clamp 1.67 r 2 r 1 1 + 0.33x10 -3 r 1 r 2 r 1 r 2 control voltage inductor current oscillator period control voltage inductor current oscillator period (a) (b) m 1 m 2 t 0 t 1 t 2 t 3 m 3 m 2 t 4 t 5 t 6 d i m 1 d i l l m 2 m 1 l l m 2 m 1 m 2 m 1 figure 21. external clock synchronization figure 22. external duty cycle clamp and multiunit synchronization figure 23. adjustable reduction of clamp level uc3842b/3b/4b/5b,uc2842b/3b page 9/16 www.first-semi.com
+ - + - s r + r r r 2r v clamp 1.67 r 2 r 1 1 i pk(max) v clamp r s 5.0v ref q bias osc ea 1.0v 5(9) 7(11) 6(10) 5(8) 3(5) r s q1 v cc v in 1(1) 2(3) 4(7) 8(14) r 1 v clamp r 2 where: 0 v clamp 1.0 v c mpsa63 t softstart in 1 v c 3v clamp c r 1 r 2 r 1 r 2 7(12) 1.0 ma comp/latch 5.0v ref + - s r q bias + 1.0ma osc r r r 2r ea 1.0v 5(9) 1(1) 2(3) 4(7) 8(14) c 1.0m t soft-start 3600c in m f figure 24. softstart circuit figure 25. adjustable buffered reduction of clamp level with softstart + - 5.0v ref + - s r q (11) (10) (8) comp/latch (5) r s 1/4 w v cc v in k m d sensefet g s power ground: to input source return control circuitry ground: to pin (9) virtually lossless current sensing can be achieved with the implementation of a sensefet power switch. for proper operation during over-current conditions, a reduction of the i pk(max) clamp level must be implemented. refer to figures 23 and 25. v pin 5 r s i pk r ds(on) r dm(on) r s if: sensefet = mtp10n10m r s = 200 then : v pin5 0.075i pk (12) figure 26. current sensing power mosfet + - 5.0v ref + - s r q 7(11) 6(10) 5(8) 3(5) r s q1 v cc v in c r the addition of the rc filter will eliminate instability caused by the leading edge spike on the current waveform. 7(12) comp/latch figure 27. current waveform spike suppression uc3842b/3b/4b/5b,uc2842b/3b page 10/16 www.first-semi.com
figure 28. mosfet parasitic oscillations 6(10) 5(8) 3(5) r s q1 v in c1 base charge removal the totem pole output can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor c 1 . s r 5.0v ref q 7(11) 6(10) 5(8) 3(5) r s q1 v cc i b + - 0 v in isolation boundary v gs waveforms + - 0 + - 0 50% dc 25% dc i p k v (pin1) 1.4 3r s n s n p comp/latch 7(12) r c n s n p + - + - bias + osc r r r 2r ea 5(9) 1(1) 2(3) 4(7) 8(14) the mcr101 scr must be selected for a holding of < 0.5 ma @ t a(min) . the simple two transistor circuit can be used in place of the scr as shown. all resistors are 10 k. mcr 101 2n 3905 2n 3903 1.0 ma s r 5.0v ref q 7(11) 6(10) 5(8) 3(5) r s q1 v cc v in series gate resistor r g will damp any high frequency parasitic oscillations caused by the mosfet input capacitance and any series wiring inductance in the gate-source circuit. 7(12) r g comp/latch + - + - figure 29. bipolar transistor drive figure 30. isolated mosfet drive figure 31. latched shutdown uc3842b/3b/4b/5b,uc2842b/3b page 11/16 www.first-semi.com
+ - + - 5.0v ref 36v s r q bias + 1.0ma osc r r r 2r ea 1.0v 7(12) 7(11) 6(10) 5(8) 3(5) r s v cc v in 1(1) 2(3) 4(7) 8(14) r t c t the buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation. m - 3.0m -m r f c f r i r d from v o r slope mps3904 5(9) comp/latch figure 32. error amplifier compensation + r 2r 1.0ma ea 2(3) 5(9) 2.5v 1(1) r f c f r d r i from v o error amp compensation circuit for stabilizing any current mode topology except for boost and flyback converters operating with continuous inductor current. r f 8.8 k + r 2r 1.0ma ea 2(3) 5(9) 2.5v 1(1) r f c f r d r p from v o error amp compensation circuit for stabilizing current mode boost and flyback topologies operating with continuous inductor current. c p r i figure 33. slope compensation uc3842b/3b/4b/5b,uc2842b/3b page 12/16 www.first-semi.com
figure 34. 27 w offline flyback regulator mur110 + - + - s r + r r 5.0v ref q bias ea 5(9) 7(11) 6(10) 5(8) 3(5) 0.5 mtp 4n50 1(1) 2(3) 4(7) 8(14) 10k 4700pf 470pf 150k 100 pf 18k 4.7k 0.01 100 + 1.0k 115 vac 4.7 w mda 202 250 56k 4.7k 3300 pf 1n4935 1n4935 ++ 68 47 1n4937 1n4937 680pf 2.7k l3 l2 l1 ++ ++ ++ 1000 1000 2200 10 10 1000 5.0v/4.0a 5.0v rtn 12v/0.3a 12v rtn -12v/0.3a primary: 45 turns #26 awg secondary 12 v: 9 turns #30 awg (2 strands) bifiliar wound secondary 5.0 v: 4 turns (six strands) #26 hexfiliar wound secondary feedback: 10 turns #30 awg (2 strands) bifiliar wound core: ferroxcube ec35-3c8 bobbin: ferroxcube ec35pcb1 gap: 0.10" for a primary inductance of 1.0 mh mur110 mbr1635 t1 22 osc t1 - 7(12) comp/latch l1 l2, l3 - 15 m h at 5.0 a, coilcraft z7156 - 25 m h at 5.0 a, coilcraft z7157 1n5819 test conditions results line regulation: 5.0 v 12 v v in = 95 to 130 vac d = 50 mv or 0.5% d = 24 mv or 0.1% load regulation: 5.0 v 12 v v in = 115 vac, i out = 1.0 a to 4.0 a v in = 115 vac, i out = 100 ma to 300 ma d = 300 mv or 3.0% d = 60 mv or 0.25% output ripple: 5.0 v 12 v v in = 115 vac 40 mv pp 80 mv pp efficiency v in = 115 vac 70% all outputs are at nominal load currents, unless otherwise noted uc3842b/3b/4b/5b,uc2842b/3b page 13/16 www.first-semi.com
sop14 dip-8 sop8 14 1 1 8 1 8 a = assembly location y = year ww = work week = device code x = 2, 3, 4or 5 ucx84xb yaww uc384xb yaww uc384xb yaww uc384xb 14 1 1 8 1 8 yaww uc284xb yaww uc284xb yaww uc284xb uc3842b/3b/4b/5b,uc2842b/3b page 14/16 www.first-semi.com marking diagpams
package dimensions dip-8 notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 sop8 seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m uc3842b/3b/4b/5b,uc2842b/3b page 15/16 www.first-semi.com
sop14 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 uc3842b/3b/4b/5b,uc2842b/3b page 16/16 www.first-semi.com package dimensions

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